1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a word line driving circuit of a dynamic random access memory device.
2. Description of the Prior Art
Recently, there has been considerable activity in the development of dynamic random access memory devices operable with a low power supply voltage in order to reduce power consumption. As the power supply voltage decreases, it becomes difficult to effectively boost word lines. Hence, it is required to obtain a high enough voltage to drive the word lines.
FIG. 1 is a circuit diagram of a conventional row decoder of a dynamic random access memory device. A plurality of row decoders respectively having the same circuit configuration as shown in FIG. 1 are provided for the respective word lines. A timing signal .phi.1 switches to a high level (equal to a bias voltage Vcc) in response to input of address data, and is applied to the drain of an n-channel field effect transistor Q1, such as a MOS transistor. A timing signal .phi.2 is applied to the gate of the transistor Q1. The timing signal .phi.2 switches from a low level (equal to the ground potential 0 V=Vss) to the high level (equal to the bias voltage Vcc) after a predetermined delay time from the fall of the level of a row address strobe (/RAS) signal. Normally, the row address strobe signal switches to the low level when it is turned ON. The symbol "/" indicates the active-low signal.
A signal .phi.5 obtained at the source of the transistor Q1 is applied to the gate of an n-channel field effect transistor Q2, such as a MOS transistor. The drain of the transistor Q2 is connected to a boost timing signal line via which a boost timing signal .phi.4 is applied to the drain of the transistor Q2. The source of the transistor Q2 is connected to a word line WL and the drain of an n-channel field effect transistor Q3, such as a MOS transistor. The source of the transistor Q2 is grounded and set at the ground potential Vss. A timing signal .phi.6, which is the inverted version of the timing signal .phi.1, is applied to the gate of the transistor Q3. An output signal .phi.3 transferred via the word line WL is controlled by the transistors Q2 and Q3. A capacitor shown in FIG. 1 is a parasitic capacitor.
The word line WL is driven in the following manner. The timing signal .phi.2 switches from the ground potential Vss to the bias potential Vcc after a predetermined delay time from the fall of the level of the row address strobe signal. Then, the timing signal .phi.1 switches from the ground potential Vss to the bias potential Vcc, and simultaneously the timing signal .phi.6 switches from the bias potential Vcc to the ground potential Vss.
In response to the above changes in the timing signals .phi.1 and .phi.6, the output signal .phi.5 of the transistor Q1 rises from the ground potential Vss to a potential (Vcc - Vth) where Vcc is the high level of the timing signal .phi.1 and Vth is the threshold voltage of the transistor Q1. In response to rising of the level of the output signal .phi.5, the transistor Q2 is turned ON. Since transistor Q3 is controlled by the inverted version .phi.6 of the timing signal .phi.1, the transistor Q3 is turned OFF when the timing signal .phi.1 switches to the high level. Hence, the output signal .phi.3 for driving the word line WL rises as the timing signal .phi.4 rises. During the above operation, the parasitic capacitor provides a so-called self-boosting function.
Conventionally, the transistors Q1, Q2 and Q3 are simultaneously produced by an identical ion implantation process. Hence, the impurity concentrations of the transistors Q1, Q2 and Q3 are the same as each other, and hence the threshold voltages of the transistors Q1, Q2 and Q3 are the same as each other.
If the bias potential Vcc is set at a potential lower than the potential shown in FIG. 2, the following problems will occur. As the bias voltage Vcc decreases, the timing signal .phi.2 applied to the gate of the transistor Q1 decreases, and hence the gate voltage of the transistor Q1 also decreases. As a result; the level of the signal .phi.5 decreases and the gate voltage of the transistor Q2 also decreases. Hence, the transistor Q2 cannot be fully turned ON, and the word line driving signal .phi.3 does not have a high enough voltage to drive the word line WL.
In order to eliminate the above problem, it may be possible to reduce the threshold voltage of the transistor Q2 and turn the transistor Q2 ON at a decreased threshold voltage. However, in this case, a leakage current will increase and a large leakage current pass will pass through the transistor Q2 and a large quantity of power will be consumed even when the transistor is OFF.
It may also be possible to increase the potential of the timing signal .phi.2 to become equal to a potential higher than the bias potential Vcc. In this case, the ON state of the transistor Q1 will be facilitated. However, this needs an additional power supply source for providing a potential higher than the bias potential Vcc.